32-input multiplexer
A five-chip, two-stage architecture built entirely from 74HC151 8-to-1 multiplexers — no other IC types allowed.
EEE student — Independent University, Bangladesh
First-year electrical and electronic engineering student. I work through circuits and digital logic during the day, and spend my own time figuring out how intelligent systems are built.
I started my BSc in Electrical and Electronic Engineering in September 2024. Most of my coursework right now is circuits, digital logic design, and the foundational math that sits underneath both.
Outside class, I'm drawn to AI and intelligent systems — not as a buzzword, but as the next layer on top of the hardware and logic I'm already learning. My goal is to eventually build things that are actually useful, not just technically interesting.
Coursework built as constrained design problems — the constraint is usually the point.
A five-chip, two-stage architecture built entirely from 74HC151 8-to-1 multiplexers — no other IC types allowed.
Parity checking across four bits using XOR gates, built on the 7486 quad XOR IC.
A Boolean circuit rebuilt using only NAND gates, derived through De Morgan's theorem and bubble-matching.
Open to conversations about EEE, AI, or anything in between.